1. Field of the Invention
The present invention relates generally to a system for enabling clock signals, and, more particularly, to a system that enables and disables clock signals based upon a lock state of a PLL circuit.
2. Description of the Related Art
There has been much investigation concerning the design of clock generating circuitry, owing in no small part to its importance in modern synchronous systems, including computing systems. Specifically, there has been some progress in the development of clock generation circuitry that meets modern day performance requirements. One requirement is that the circuitry only output clock signals having stable frequencies. Moreover, another requirement is that such circuitry output only valid frequencies. In a common configuration, a phase locked loop (PLL) circuit is employed to generate an output reference signal that is phase locked relative to an input reference signal.
One design approach taken in the art has been merely to use the output reference signal of the PLL as an output clock. This approach has, depending on the application, several shortcomings, not the least of which includes the existence of a condition where the output reference signal is neither of a valid frequency, nor is stable. This situation almost always occurs when the device containing such clock generation circuitry is initially powered up. By way of background, it is fairly well known that a PLL circuit is characterized by an overall transfer function. Accordingly, before a voltage controlled oscillator (VCO) portion (or equivalents thereof) of the PLL locks its output to the PLL input reference signal, a period elapses wherein the VCO output signal oscillates, relative to the input reference signal (i.e., it undershoots, and overshoots the input reference signal). Thus, before a steady state, phase-locked condition is achieved, an interval known as a "pull in" or "settling" interval occurs. Thus, it should be appreciated that although the output of the PLL may be at a valid frequency (temporarily), such frequency is not stable, but rather, may only be a transitory condition. This condition, although perhaps lasting several clock cycles, is not a steady-state phase-locked condition. Therefore, directly using a PLL output may be undesirable for certain applications.
Another approach taken in the art has addressed the above-described power up oscillation. This approach selectively enables and disables the output clock signal for preselected intervals (fixed and arbitrarily selected). The structure for accomplishing this may include a conventional power-on-reset circuit, used in combination with a delay circuit. The conventional power-on-reset circuit may generally be formed using resistor chains, and provides a low-level output until the power supply has reached a predetermined operating level, and has stabilized, at which time it outputs a high level signal. This high level signal is then delayed by a predetermined amount by the delay circuit. The delay circuit output is then used to enable and disable clock signals.
One disadvantage of this approach is that, unless the enabling circuitry is very conservatively designed, the output clock signal may be permitted to be generated, even though the PLL is not phase locked. In particular, the predetermined amount of delay inserted by the delay circuit, in addition to the delay associated with the conventional power-on-reset circuit, must be selected to be long enough to accommodate the worst case PLL lock time. This is not a good solution since the overall design of such a circuit with an adequate delay is fairly difficult. Further, in some cases, the output clock signal will still be disabled, even though the PLL has, in fact, reached "lock".
Moreover, the use of the conventional power-on-reset circuitry may introduce reliability problems into the operation of the overall circuit. Specifically, the above-referred to conventional approach for designing power-on-reset circuits (resistor chains) may result in a device that exhibits performance parameters (i.e., trip levels) that are undesirably variable across both fabrication process variations, as well as temperature (operating) variations. Thus, the power-on-reset circuit could, under some circumstances, trip at a level that is either too high or too low. For purposes of illustration only, assume that for a 3.3 volt device, a conventional setup specifies a nominal power-on-reset trip point of 2 volts. However, due to the above-described undesirable variations in performance, the power-on-reset circuit may, in fact, trip at 3.0 volts. Further, in a common configuration, a 3.3 volt part may be specified to operate within a range of between 3.0-3.6 volts. Thus, an undesirable situation arises wherein the circuit could trip even though the power supply is operating within specification. Finally, the conventional approach using conventional power-on-reset circuits only works during power-up of the device.
Thus, there is a need to provide an improved system for enabling, and disabling clock signals that minimizes or eliminates one or more of the problems as described above.